To decrease the fabrication time and therefore to decrease the cost of forming integrated circuits, the number of masking steps, etching steps, doping steps, and drive-in steps should be held to a minimum. In addition, the number of critical mask alignments, where one mask pattern must be precisely aligned with respect to another mask pattern, should also be held to a minimum to simplify the fabrication process. Therefore, any processes which form circuit components using less and/or simpler process steps than those already used to form the circuit components are very valuable.
It is often desirable to form both PNP and NPN bipolar transistors on a same substrate. When forming a lateral PNP bipolar transistor on a same substrate as an NPN bipolar transistor (whether vertical or lateral), it has been known to form the P+ collector and emitter regions of the lateral PNP transistor using the same masking, doping, and drive-in steps as used to form a P+ base region of the NPN transistor. Such a resulting structure is illustrated in FIG. 1.
Generally, to form the structure of FIG. 1, an N- epitaxial layer 10 is deposited or grown over a P- substrate 12 and N+ buried layer regions 13.
A masking, etching, doping, and drive-in step is used to form the highly conductive and deep P++ isolation region 14, which isolates one portion of epitaxial layer 10 from another portion. Such a portion isolated by isolation region 14 is sometimes referred to as a tub. Isolation region 14 is formed so as to make contact with the underlying P- substrate 12.
After isolation region 14 is formed, a next masking, etching, doping, and drive-in process is conducted to deposit and drive-in P-type dopants to concurrently form the P+ contact region for isolation region 14, the P+ collector and emitter regions of the PNP lateral transistor, and the P+ base region of the NPN transistor. These regions, after drive-in, are identified in FIG. 1 as P+ regions 15, 16, 17, and 18, respectively. Although the cross-section of FIG. 1 shows two collector regions 16, these regions 16 are part of a same ring and are thus considered one region.
Since these P+ regions 15-18 are all formed in the same process, they must all have the same conductivity and depth. It is well known that the efficiency (i.e, gain) of a transistor is increased by providing a more lightly doped base. The efficiency is also increased by providing a more heavily doped emitter region. Therefore, when using the above-described method to form the structure of FIG. 1, a trade-off must be made between the doping concentration of the NPN base region 18 and the doping concentration of the PNP emitter region 17. Therefore, although a desirable NPN base conductivity may be in the range of 100-200 ohms/square, a similar PNP emitter conductivity will result in a very poor high current emitter. Accordingly, the method for forming the structure of FIG. 1 is used where highly efficient PNP and NPN transistors are not required.
After the formation of the P+ regions in FIG. 1, a next masking, etching, doping, and drive-in step is then used to form an N++ contact region 22 (to enable ohmic contact with N- epitaxial layer 10) and to form an N+ emitter region 24 for the NPN transistor.
If a more efficient PNP and NPN transistor are desired to be formed, the emitter region of the PNP transistor must be formed in a separate masking and doping step than used to form the P-type base region of the NPN transistor so that the emitter and base regions will each have the desired doping concentrations. FIGS. 2A-2C illustrate one method for forming the base region and the emitter region in separate masking and doping steps.
In FIG. 2A, after a P++ isolation region 26 is formed, epitaxial layer 10 is masked and etched so as to expose regions designated as 28, 29, and 30 where it is desired to inject P-type dopants (e.g., boron) into the surface of epitaxial layer 10 to form the highly conductive collector and emitter regions for a lateral PNP transistor. The P-type dopants are then injected or otherwise deposited into the exposed surface of the epitaxial layer 10. The deposited dopants are then driven-in. During this drive-in step, the epitaxial layer 10 is oxidized in preparation for a next masking step, since any oxide over regions 28-30 was removed in the previous masking and etching step.
FIG. 2A shows the portion of an oxide layer 32 grown over the non-etched portion of N- epitaxial layer 10 being thicker than the oxide layer 32 grown directly over the various P++ regions 34, 35, and 36.
After this first series of steps illustrated with respect to FIG. 2A, a next masking and etching step is conducted to expose a contact region 37 for the isolation region 26 and to expose the portion of epitaxial layer 10 to the right of isolation region 26 where the P-type base region for the NPN transistor is to be formed. This exposed NPN base region is designated as region 38 in FIG. 2B. P-type dopants are then deposited in the exposed surface portions of epitaxial layer 10 to the desired concentration for the formation of an NPN base region 40 and to increase the P-type doping in the contact region 37.
After this step of depositing dopants, the dopants are driven-in, and the surface of the wafer is again oxidized. This adds more oxide to the already existing layer of oxide 32 shown in FIG. 2A and grows a first layer of oxide 42 over the exposed base region 40 and contact region 37.
To now form the N++ emitter region for the NPN transistor and to optionally form an N++ contact region for the N- epitaxial layer 10, a next masking, etching, and doping step is conducted to form an N++ emitter region 46 in base region 40 and to form an N++ epitaxial layer contact region 48. Typically, N-type phosphorus dopants are used, although arsenic or antimony dopants may be used for certain applications.
After this masking, etching, and doping step, the dopants are then again driven-in, and the surface of the wafer is again oxidized so that additional oxide is again grown over the existing layer of oxide 32, and a first layer of oxide 50 is grown over the exposed N++ regions 46 and 48.
The resulting structure of FIG. 2C has a number of drawbacks associated with it. One drawback is that contact holes through the oxide above each of the regions in epitaxial layer 10 must be patterned and etched so that metal may be deposited and provide ohmic contact to each of the regions. Since the oxide over each of the regions has a different thickness, contact hole etching may result in either an improperly sloped contact over the thinnest oxide or a marginally completed contact etched over the thickest oxide.
Additionally, the alignment of this contact hole mask is critical, since the contact pattern must properly align to all the regions simultaneously. This requires tradeoffs on the contact hole mask alignment with respect to all regions in the surface of epitaxial layer 10. Since N++ emitter region 46, P base region 40, P+ contact region 37, and P++ regions 34-36 are formed using three different masks, the alignment of the contact hole mask to, for example, N++ emitter region 46 will result in a certain amount of non-alignment with base region 40, and the regions 34-37.
Accordingly, there are three masking alignment tolerances that must be strictly adhered to when forming the structure of FIG. 2C. These three masking alignments are all critical for the contact hole mask to properly align with all regions formed in epitaxial layer 10 of FIG. 2C.
Other drawbacks exist which make the process described above time consuming and inefficient.
What is needed is an improved method to form a lateral PNP transistor in a same substrate as an NPN transistor which does not have the above-described drawbacks of prior art methods.